1. Field of the Invention
The present invention relates to an inverter, and, more particularly, to an inverter with extremely fast switching characteristics and which may be used as a building block in numerous high speed circuit applications.
2. Description of the Prior Art
The CMOS inverter is a basic building block in modem microelectronics. Multiple inverters are used to construct standard logic gates such as NAND gates and NOR gates. Inverters may also be used for numerous other applications, such as a clock generator circuit or a decoder circuit.
A standard CMOS inverter includes an NMOS transistor and a PMOS transistor. The gates of the two transistors are coupled to an input node. The source-drain current channel of the PMOS transistor is coupled between Vcc and an output node. The source-drain current path of the NMOS transistor is coupled between the output node and ground. When a logical high signal is applied to the input node, the PMOS transistor is turned off and the NMOS transistor is turned on. As a result, the output node is inverted and pulled down to ground. When a logical low signal is applied to the input node, the complement of the above occurs and the output node is pulled up to Vcc.
The standard CMOS inverter has a significant problem regarding switching speed. For a given channel width and turn on voltage, an NMOS transistor is approximately twice as conductive as a PMOS transistor. To ensure that the inverter has approximately the same delay for both high to low and low to high transitions, the channel width of the PMOS transistor is typically made twice as large as the NMOS transistor. As a consequence, for any given input signal, one third (1/3) of the charge is used to drive the NMOS transistor and two thirds (2/3) of the charge is used to drive the PMOS transistor. The switching speed of the CMOS inverter is impaired because a significant portion of the available charge is used to perform non-productive work, i.e., the turning off of one of the transistors. The conventional CMOS inverter is therefore no longer ideal for use in many circuit applications, such as high speed microprocessors.
A form of CMOS circuitry with improved speed characteristics is the "post charge logic" technique described in U.S. Pat. No. 4,985,643 to Robert J. Proebsting. This patent describes a chain of logic stages. Each stage includes a set transistor and a reset transistor. The set transistor of each stage is responsible for forward propagating an input pulse through the chain. In one embodiment, the reset of each stage is accomplished by a feedback signal from a set transistor of a subsequent stage in the chain. In a second embodiment, a four stage inverter chain (hereafter referred to as a reset chain) is used to reset each stage. The reset chain receives an active pulse during the set phase of the stage, and, four delays later, the pulse is used to reset the stage in anticipation of the next pulse. Both configurations have the advantage of eliminating the need of turning off the reset transistor of an active stage while forward propagating the signal pulse through the set transistor of that stage. The two post charge logic configurations, however, have significant disadvantages.
In the feedback embodiment, a metal trace feedback interconnect is required for every stage in the chain. Numerous metal trace feedback paths are very complicated and difficult to lay out and use up valuable space on the die. Another drawback is that a portion of the forward propagation signal, albeit less than in convention CMOS, is still being used for non-productive work. For each stage, a certain percentage of the available energy is used to reset a previous stage via the feedback interconnect. Finally, given that a particular stage is responsible for driving a subsequent stage, a reset node of a previous stage, and in some situations, a circuit load, a circuit designer must calculate the fanout delay of the particular stage to equal that of the other stages in the chain. This can be a time-consuming task with chips that contain a large number of post charge logic circuits and stages.
The inverter chain embodiment also has a number of drawbacks. A total of four conventional inverters, (equivalent to eight transistors) is required for each reset chain of each stage. These additional transistors may use up valuable space on the die, creating lay out problems. In certain applications, these additional transistors may also consume the limited power available on the chip. It is also very difficult to tune each reset chain so that the reset time period for each stage is the same. As you progress down the chain of stages, the transistors of each stage (including the reset chain) generally become physically larger. Temperature variations, process variations, variations in supply voltage and the differences in the rise and fall time of the input signals also affect the switching speed of the transistors. Each of these factors complicate the tuning process.
In a complex circuit with many post charge logic stages, the effort to overcome the fan out delay and/or the tuning problems is burdensome. A substantial amount of time is required to determine the optimal size and switching characteristics of the transistors in the post charge logic circuit. Many circuit designers have thus been discouraged from using this technique.